1. Field of the Invention
The present invention relates to a semiconductor memory device such as a DRAM. In particular, the present invention relates to a bit line kicker control circuit provided for improving a read margin when reading “H” data from a memory cell.
2. Description of the Related Art
In the DRAM, device micro-fabrication and low power supply voltage have been growing, while it is difficult to secure a capacitance of a memory cell capacitor. The capacitance of the memory cell capacitor requires a margin capacitance in addition to a capacitance equivalent to a lower limit read signal of the sense amplifier sensitivity. In the margin capacitance, the following many factors must be taken into consideration. That is, the factors are non-uniformity of bit line capacitance by the processing non-uniformity of the bit line, various noises of cell array sections, charge leak in PN-junction of cell transistors, data write shortage by threshold dispersion of cell transistors, soft error resistance, etc.
The charge leak in the PN-junction of memory cell results from a recombination current generated in a depletion layer. For this reason, in an “H” data hold time, a leak current from a memory cell is larger than that in an “L” data hold time. In general, since a memory cell transistor of the DRAM is formed of an NMOS transistor, “H” data write shortage by dispersion of the threshold voltage of the memory cell transistor is the problem relevant to “H” data only. Thus, the “H” data has many factors of decreasing a read signal as compared with the “L” data.
For this reason, only when the hold data of the memory cell is an “H” level, a method of increasing the signal read from the memory cell is required. To give an example of the method, until the sense amplifier operation starts after the bit line equalizing operation is released, a potential of only the reference side bit line of the bit line pair is reduced so as to improve a read margin of the “H” data; a so-called bit line kicker technique has been known. According to the above technique, one terminal of a capacitor called a bit line kicker is connected to a bit line; the other terminal thereof is connected to an output node of a driver circuit called a bit line kicker driver. The driver circuit drives the bit line kicker driver so that the bit line potential can be changed.
However, in the conventional case, many control signals must be inputted to the bit line kicker driver; for this reason, it is difficult to dispersedly arrange the bit line kicker driver on a memory core section having no sufficient margin in layout area. As a result, the bit line kicker driver must be arranged on only outer peripheral portions of the core. This problem will be described below in detail.
FIG. 1 shows a circuit configuration of a bit line kicker driver of a conventional DRAM. When a complementary bit line pair is provided as a bit line, a pair of bit line kicker driver lines BLkick t and BLkick c is provided. In FIG. 1, there are shown two pairs of bit line kicker driver lines BLkick t and BLkick c. A pair of bit line kicker drivers 10t and 10c for driving the bit line kicker driver lines BLkick t and BLkick c is arranged for each sense amplifier of a memory cell array.
A decode circuit 11 is provided for each sense amplifier. The decode circuit 11 decodes two kinds of address signals Addr A<0>, Addr A<1>, . . . Addr A<n> and Addr B<0>, Addr B<1>, . . . Addr B<n>, which are positional information of a sense amplifier to be activated. An output of the decode circuit 11 is inputted to the corresponding pair of bit line kicker drivers 10t and 10c in parallel. By doing so, the desired pair of bit line kicker drivers 10t and 10c corresponding to the sense amplifier to be activated is selected.
A set signal Set is used to designate an activation timing of the pair of bit line kicker drivers 10t and 10c. A reset signal Reset is used to designate a non-activation timing of the pair of bit line kicker drivers 10t and 10c. Select signals Sel t and Sel c are used to select which of the pair of bit line kicker drivers 10t and 10c in order to determine whether the bit line kicker driver connected to which of the bit line pair BL t or BL c should be driven.
As described above, in the conventional case, the signals decoding address signals, the set signal Set, the reset signal Reset and the select signals Sel t and Sel c for selecting desired one bit line kicker driver are inputted to the bit line kicker drivers 10t and 10c. For this reason, many control signals must be connected to the bit line kicker drivers 10t and 10c. As a result, it is difficult to dispersedly arrange the bit line kicker driver on a memory core section; therefore, the bit line kicker driver must be arranged on only outer peripheral portions of the core. Consequently, it is difficult to operate the bit line kicker driver line at high speed, and it is desired to solve the above problem.